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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_maccontrol.v] - Rev 338

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338 root 4191d 01h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
335 New directory structure. root 4248d 07h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 6487d 04h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6547d 15h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 6548d 16h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6549d 23h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
37 Link in the header changed. mohor 6850d 06h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6946d 08h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7020d 02h /ethmac/tags/rel_14/rtl/verilog/eth_maccontrol.v

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