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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_miim.v] - Rev 15

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15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7059d 17h /ethmac/tags/rel_14/rtl/verilog/eth_miim.v

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