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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_rxethmac.v] - Rev 338

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Rev Log message Author Age Path
338 root 5467d 03h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
335 New directory structure. root 5524d 09h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7763d 06h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7823d 17h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7826d 01h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8102d 11h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
62 RxAbort is an output. No need to have is declared as wire. mohor 8103d 05h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
58 File format changed. mohor 8103d 07h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
53 Addition of new module eth_addrcheck.v billditt 8103d 22h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
37 Link in the header changed. mohor 8126d 08h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8222d 10h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
18 Few little NCSIM warnings fixed. mohor 8260d 04h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8296d 04h /ethmac/tags/rel_14/rtl/verilog/eth_rxethmac.v

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