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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 271

Rev	Log message	Author	Age	Path
271	This commit was manufactured by cvs2svn to create tag 'rel_14'.		7764d 07h	/ethmac/tags/rel_14/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	7859d 02h	/ethmac/tags/rel_14/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	7867d 02h	/ethmac/tags/rel_14/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7884d 01h	/ethmac/tags/rel_14/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7946d 02h	/ethmac/tags/rel_14/rtl/verilog/eth_spram_256x32.v