OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 4192d 13h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
335 New directory structure. root 4249d 18h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 6488d 16h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6488d 16h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 6489d 16h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 6548d 14h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6549d 02h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6551d 10h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6557d 06h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 6583d 07h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 6583d 11h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6583d 12h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6587d 12h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6590d 12h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 6591d 11h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 6620d 14h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 6621d 14h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 6621d 17h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 6623d 11h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 6627d 09h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 6648d 08h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6668d 09h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6670d 12h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 6674d 03h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6675d 12h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 6683d 01h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6683d 15h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.
mohor 6684d 04h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 6684d 07h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6751d 18h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.