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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

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134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 6650d 10h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6670d 11h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6672d 14h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 6676d 04h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6677d 13h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 6685d 02h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6685d 16h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.
mohor 6686d 05h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 6686d 08h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6753d 19h /ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v

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