OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] - Rev 226

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7859d 06h /ethmac/tags/rel_15/
225 Some minor changes. tadejm 7859d 06h /ethmac/tags/rel_15/
224 Signals for a wave window in Modelsim. tadejm 7859d 07h /ethmac/tags/rel_15/
223 Some code changed due to bug fixes. tadejm 7859d 07h /ethmac/tags/rel_15/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7863d 05h /ethmac/tags/rel_15/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7866d 06h /ethmac/tags/rel_15/
218 Typo error fixed. (When using Bist) mohor 7866d 08h /ethmac/tags/rel_15/
217 Bist supported. mohor 7866d 08h /ethmac/tags/rel_15/
216 Bist signals added. mohor 7866d 08h /ethmac/tags/rel_15/
215 Bist supported. mohor 7866d 09h /ethmac/tags/rel_15/
214 Signals for WISHBONE B3 compliant interface added. mohor 7867d 05h /ethmac/tags/rel_15/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7867d 05h /ethmac/tags/rel_15/
212 Minor $display change. mohor 7867d 05h /ethmac/tags/rel_15/
211 Bist added. mohor 7867d 05h /ethmac/tags/rel_15/
210 BIST added. mohor 7867d 05h /ethmac/tags/rel_15/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7868d 08h /ethmac/tags/rel_15/
208 Virtual Silicon RAMs moved to lib directory tadej 7884d 02h /ethmac/tags/rel_15/
207 Virtual Silicon RAM support fixed tadej 7884d 02h /ethmac/tags/rel_15/
206 Virtual Silicon RAM added to the simulation. mohor 7884d 02h /ethmac/tags/rel_15/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7884d 03h /ethmac/tags/rel_15/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7884d 03h /ethmac/tags/rel_15/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7884d 03h /ethmac/tags/rel_15/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7887d 04h /ethmac/tags/rel_15/
201 Core size added to the document. mohor 7887d 05h /ethmac/tags/rel_15/
200 File with lower case checked in instead. mohor 7887d 05h /ethmac/tags/rel_15/
199 Datasheet name changed to lower case name. mohor 7887d 05h /ethmac/tags/rel_15/
198 Removed file. File with name in lower case will be added instead. mohor 7887d 05h /ethmac/tags/rel_15/
197 Ethernet Data Sheet. mohor 7887d 05h /ethmac/tags/rel_15/
196 Ethernet product brief. mohor 7887d 06h /ethmac/tags/rel_15/
195 Product brief removed because it is the same as Datasheet. mohor 7887d 06h /ethmac/tags/rel_15/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.