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Rev Log message Author Age Path
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6151d 23h /ethmac/tags/rel_15/
252 Just some updates. tadejm 6151d 23h /ethmac/tags/rel_15/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6151d 23h /ethmac/tags/rel_15/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6151d 23h /ethmac/tags/rel_15/
248 wb_rst_i is used for MIIM reset. mohor 6152d 23h /ethmac/tags/rel_15/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6156d 03h /ethmac/tags/rel_15/
245 Rev 1.7. mohor 6156d 20h /ethmac/tags/rel_15/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6156d 22h /ethmac/tags/rel_15/
243 Late collision is not reported any more. tadejm 6157d 04h /ethmac/tags/rel_15/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6157d 18h /ethmac/tags/rel_15/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6157d 19h /ethmac/tags/rel_15/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6157d 19h /ethmac/tags/rel_15/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6157d 19h /ethmac/tags/rel_15/
238 Defines fixed to use generic RAM by default. mohor 6169d 23h /ethmac/tags/rel_15/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6172d 04h /ethmac/tags/rel_15/
235 rev 4. mohor 6172d 19h /ethmac/tags/rel_15/
234 Figure list assed to the revision 3. mohor 6173d 03h /ethmac/tags/rel_15/
233 Revision 0.3 released. Some figures added. mohor 6173d 03h /ethmac/tags/rel_15/
232 fpga define added. mohor 6177d 22h /ethmac/tags/rel_15/
231 Description of Core Modules added (figure). mohor 6179d 23h /ethmac/tags/rel_15/
229 case changed to casex. mohor 6183d 20h /ethmac/tags/rel_15/
227 Changed BIST scan signals. tadejm 6184d 00h /ethmac/tags/rel_15/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6184d 01h /ethmac/tags/rel_15/
225 Some minor changes. tadejm 6184d 01h /ethmac/tags/rel_15/
224 Signals for a wave window in Modelsim. tadejm 6184d 03h /ethmac/tags/rel_15/
223 Some code changed due to bug fixes. tadejm 6184d 03h /ethmac/tags/rel_15/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6188d 01h /ethmac/tags/rel_15/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6191d 01h /ethmac/tags/rel_15/
218 Typo error fixed. (When using Bist) mohor 6191d 03h /ethmac/tags/rel_15/
217 Bist supported. mohor 6191d 03h /ethmac/tags/rel_15/

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