OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] - Rev 253

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7825d 15h /ethmac/tags/rel_15
252 Just some updates. tadejm 7825d 15h /ethmac/tags/rel_15
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7825d 15h /ethmac/tags/rel_15
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7825d 15h /ethmac/tags/rel_15
248 wb_rst_i is used for MIIM reset. mohor 7826d 15h /ethmac/tags/rel_15
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7829d 18h /ethmac/tags/rel_15
245 Rev 1.7. mohor 7830d 12h /ethmac/tags/rel_15
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7830d 14h /ethmac/tags/rel_15
243 Late collision is not reported any more. tadejm 7830d 20h /ethmac/tags/rel_15
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7831d 10h /ethmac/tags/rel_15
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7831d 10h /ethmac/tags/rel_15
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7831d 10h /ethmac/tags/rel_15
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7831d 11h /ethmac/tags/rel_15
238 Defines fixed to use generic RAM by default. mohor 7843d 15h /ethmac/tags/rel_15
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7845d 20h /ethmac/tags/rel_15
235 rev 4. mohor 7846d 11h /ethmac/tags/rel_15
234 Figure list assed to the revision 3. mohor 7846d 19h /ethmac/tags/rel_15
233 Revision 0.3 released. Some figures added. mohor 7846d 19h /ethmac/tags/rel_15
232 fpga define added. mohor 7851d 14h /ethmac/tags/rel_15
231 Description of Core Modules added (figure). mohor 7853d 15h /ethmac/tags/rel_15

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.