OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] - Rev 262

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.
mohor 6180d 03h /ethmac/tags/rel_15/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6180d 03h /ethmac/tags/rel_15/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 6180d 15h /ethmac/tags/rel_15/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 6181d 04h /ethmac/tags/rel_15/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 6181d 05h /ethmac/tags/rel_15/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 6181d 05h /ethmac/tags/rel_15/
255 TPauseRq synchronized to tx_clk. mohor 6181d 05h /ethmac/tags/rel_15/
254 Temp version. mohor 6182d 08h /ethmac/tags/rel_15/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6182d 11h /ethmac/tags/rel_15/
252 Just some updates. tadejm 6182d 11h /ethmac/tags/rel_15/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6182d 11h /ethmac/tags/rel_15/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6182d 11h /ethmac/tags/rel_15/
248 wb_rst_i is used for MIIM reset. mohor 6183d 11h /ethmac/tags/rel_15/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6186d 14h /ethmac/tags/rel_15/
245 Rev 1.7. mohor 6187d 08h /ethmac/tags/rel_15/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6187d 10h /ethmac/tags/rel_15/
243 Late collision is not reported any more. tadejm 6187d 16h /ethmac/tags/rel_15/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6188d 06h /ethmac/tags/rel_15/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6188d 06h /ethmac/tags/rel_15/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6188d 06h /ethmac/tags/rel_15/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.