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338 root 3790d 02h /ethmac/tags/rel_15
335 New directory structure. root 3847d 08h /ethmac/tags/rel_15
273 This commit was manufactured by cvs2svn to create tag 'rel_15'. 6085d 04h /ethmac/tags/rel_15
272 When control packets were received, they were ignored in some cases. tadejm 6085d 04h /ethmac/tags/rel_15
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6086d 06h /ethmac/tags/rel_15
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 6087d 06h /ethmac/tags/rel_15
268 Release 1.19. Control frame description changed. mohor 6140d 23h /ethmac/tags/rel_15
267 Full duplex control frames tested. mohor 6141d 01h /ethmac/tags/rel_15
266 Flow control test almost finished. mohor 6146d 00h /ethmac/tags/rel_15
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 6146d 04h /ethmac/tags/rel_15
263 test_mac_full_duplex_flow_control tests pretty much finished.
FRM. AT 4 TX BD ( 10Mbps ) finished.
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 6146d 15h /ethmac/tags/rel_15
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.
mohor 6146d 16h /ethmac/tags/rel_15
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 6146d 16h /ethmac/tags/rel_15
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
mohor 6147d 04h /ethmac/tags/rel_15
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 6147d 17h /ethmac/tags/rel_15
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 6147d 17h /ethmac/tags/rel_15
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 6147d 17h /ethmac/tags/rel_15
255 TPauseRq synchronized to tx_clk. mohor 6147d 18h /ethmac/tags/rel_15
254 Temp version. mohor 6148d 21h /ethmac/tags/rel_15
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6148d 23h /ethmac/tags/rel_15
252 Just some updates. tadejm 6149d 00h /ethmac/tags/rel_15
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6149d 00h /ethmac/tags/rel_15
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6149d 00h /ethmac/tags/rel_15
248 wb_rst_i is used for MIIM reset. mohor 6150d 00h /ethmac/tags/rel_15
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6153d 03h /ethmac/tags/rel_15
245 Rev 1.7. mohor 6153d 21h /ethmac/tags/rel_15
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6153d 23h /ethmac/tags/rel_15
243 Late collision is not reported any more. tadejm 6154d 04h /ethmac/tags/rel_15
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6154d 19h /ethmac/tags/rel_15
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6154d 19h /ethmac/tags/rel_15

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