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252 Just some updates. tadejm 6151d 04h /ethmac/tags/rel_15
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6151d 04h /ethmac/tags/rel_15
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6151d 04h /ethmac/tags/rel_15
248 wb_rst_i is used for MIIM reset. mohor 6152d 04h /ethmac/tags/rel_15
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6155d 08h /ethmac/tags/rel_15
245 Rev 1.7. mohor 6156d 01h /ethmac/tags/rel_15
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6156d 03h /ethmac/tags/rel_15
243 Late collision is not reported any more. tadejm 6156d 09h /ethmac/tags/rel_15
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6156d 23h /ethmac/tags/rel_15
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6157d 00h /ethmac/tags/rel_15

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