OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] [bench/] - Rev 158

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 Typo fixed. mohor 7385d 19h /ethmac/tags/rel_15/bench/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7388d 01h /ethmac/tags/rel_15/bench/
156 Valid testbench. mohor 7388d 01h /ethmac/tags/rel_15/bench/
155 Minor changes. mohor 7388d 01h /ethmac/tags/rel_15/bench/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7430d 18h /ethmac/tags/rel_15/bench/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7432d 19h /ethmac/tags/rel_15/bench/
117 Clock mrx_clk set to 2.5 MHz. mohor 7436d 22h /ethmac/tags/rel_15/bench/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7436d 22h /ethmac/tags/rel_15/bench/
108 Testbench supports unaligned accesses. mohor 7514d 01h /ethmac/tags/rel_15/bench/
107 TX_BUF_BASE changed. mohor 7514d 01h /ethmac/tags/rel_15/bench/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 7558d 23h /ethmac/tags/rel_15/bench/
80 Small fixes for external/internal DMA missmatches. mohor 7579d 19h /ethmac/tags/rel_15/bench/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 7589d 23h /ethmac/tags/rel_15/bench/
66 Testbench fixed, code simplified, unused signals removed. mohor 7590d 04h /ethmac/tags/rel_15/bench/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 7591d 15h /ethmac/tags/rel_15/bench/
49 HASH0 and HASH1 register read/write added. mohor 7593d 15h /ethmac/tags/rel_15/bench/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 7599d 21h /ethmac/tags/rel_15/bench/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 7659d 23h /ethmac/tags/rel_15/bench/
23 Number of addresses (wb_adr_i) minimized. mohor 7710d 00h /ethmac/tags/rel_15/bench/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7710d 03h /ethmac/tags/rel_15/bench/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.