OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] [rtl/] - Rev 255

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
255 TPauseRq synchronized to tx_clk. mohor 7820d 16h /ethmac/tags/rel_15/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7821d 22h /ethmac/tags/rel_15/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7821d 23h /ethmac/tags/rel_15/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7821d 23h /ethmac/tags/rel_15/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7822d 23h /ethmac/tags/rel_15/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7826d 02h /ethmac/tags/rel_15/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7826d 22h /ethmac/tags/rel_15/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7827d 18h /ethmac/tags/rel_15/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7827d 18h /ethmac/tags/rel_15/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7827d 18h /ethmac/tags/rel_15/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7827d 18h /ethmac/tags/rel_15/rtl/
238 Defines fixed to use generic RAM by default. mohor 7839d 22h /ethmac/tags/rel_15/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7842d 03h /ethmac/tags/rel_15/rtl/
232 fpga define added. mohor 7847d 21h /ethmac/tags/rel_15/rtl/
229 case changed to casex. mohor 7853d 19h /ethmac/tags/rel_15/rtl/
227 Changed BIST scan signals. tadejm 7853d 23h /ethmac/tags/rel_15/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7854d 01h /ethmac/tags/rel_15/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7858d 00h /ethmac/tags/rel_15/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7861d 01h /ethmac/tags/rel_15/rtl/
218 Typo error fixed. (When using Bist) mohor 7861d 03h /ethmac/tags/rel_15/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7861d 23h /ethmac/tags/rel_15/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7861d 23h /ethmac/tags/rel_15/rtl/
212 Minor $display change. mohor 7862d 00h /ethmac/tags/rel_15/rtl/
211 Bist added. mohor 7862d 00h /ethmac/tags/rel_15/rtl/
210 BIST added. mohor 7862d 00h /ethmac/tags/rel_15/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7878d 22h /ethmac/tags/rel_15/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7878d 22h /ethmac/tags/rel_15/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7881d 23h /ethmac/tags/rel_15/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7890d 01h /ethmac/tags/rel_15/rtl/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7891d 02h /ethmac/tags/rel_15/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.