URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
338		root	5468d 15h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
335	New directory structure.	root	5525d 20h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
273	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7763d 17h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7827d 12h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7831d 16h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
238	Defines fixed to use generic RAM by default.	mohor	7845d 12h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
232	fpga define added.	mohor	7853d 11h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7867d 14h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
211	Bist added.	mohor	7867d 14h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7884d 12h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7903d 12h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7922d 08h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7924d 11h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7946d 15h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8027d 20h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8036d 21h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8072d 17h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
73	Number of interrupts changed	mohor	8093d 14h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
68	Registered trimmed. Unused registers removed.	mohor	8103d 16h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8103d 17h	/ethmac/tags/rel_15/rtl/verilog/eth_defines.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

Filtering Options