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246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6483d 01h /ethmac/tags/rel_17/
245 Rev 1.7. mohor 6483d 19h /ethmac/tags/rel_17/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6483d 21h /ethmac/tags/rel_17/
243 Late collision is not reported any more. tadejm 6484d 03h /ethmac/tags/rel_17/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6484d 17h /ethmac/tags/rel_17/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6484d 17h /ethmac/tags/rel_17/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6484d 17h /ethmac/tags/rel_17/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6484d 17h /ethmac/tags/rel_17/
238 Defines fixed to use generic RAM by default. mohor 6496d 22h /ethmac/tags/rel_17/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6499d 03h /ethmac/tags/rel_17/
235 rev 4. mohor 6499d 17h /ethmac/tags/rel_17/
234 Figure list assed to the revision 3. mohor 6500d 02h /ethmac/tags/rel_17/
233 Revision 0.3 released. Some figures added. mohor 6500d 02h /ethmac/tags/rel_17/
232 fpga define added. mohor 6504d 21h /ethmac/tags/rel_17/
231 Description of Core Modules added (figure). mohor 6506d 22h /ethmac/tags/rel_17/
229 case changed to casex. mohor 6510d 19h /ethmac/tags/rel_17/
227 Changed BIST scan signals. tadejm 6510d 23h /ethmac/tags/rel_17/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6511d 00h /ethmac/tags/rel_17/
225 Some minor changes. tadejm 6511d 00h /ethmac/tags/rel_17/
224 Signals for a wave window in Modelsim. tadejm 6511d 02h /ethmac/tags/rel_17/
223 Some code changed due to bug fixes. tadejm 6511d 02h /ethmac/tags/rel_17/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6515d 00h /ethmac/tags/rel_17/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6518d 00h /ethmac/tags/rel_17/
218 Typo error fixed. (When using Bist) mohor 6518d 02h /ethmac/tags/rel_17/
217 Bist supported. mohor 6518d 02h /ethmac/tags/rel_17/
216 Bist signals added. mohor 6518d 02h /ethmac/tags/rel_17/
215 Bist supported. mohor 6518d 03h /ethmac/tags/rel_17/
214 Signals for WISHBONE B3 compliant interface added. mohor 6518d 23h /ethmac/tags/rel_17/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6518d 23h /ethmac/tags/rel_17/
212 Minor $display change. mohor 6518d 23h /ethmac/tags/rel_17/

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