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[/] [ethmac/] [tags/] [rel_17/] [rtl/] - Rev 272

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Rev Log message Author Age Path
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7839d 06h /ethmac/tags/rel_17/rtl/
232 fpga define added. mohor 7845d 00h /ethmac/tags/rel_17/rtl/
229 case changed to casex. mohor 7850d 22h /ethmac/tags/rel_17/rtl/
227 Changed BIST scan signals. tadejm 7851d 01h /ethmac/tags/rel_17/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7851d 03h /ethmac/tags/rel_17/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7855d 02h /ethmac/tags/rel_17/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7858d 03h /ethmac/tags/rel_17/rtl/
218 Typo error fixed. (When using Bist) mohor 7858d 05h /ethmac/tags/rel_17/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7859d 02h /ethmac/tags/rel_17/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7859d 02h /ethmac/tags/rel_17/rtl/

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