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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 272

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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6600d 16h /ethmac/tags/rel_17/rtl/verilog/
232 fpga define added. mohor 6606d 10h /ethmac/tags/rel_17/rtl/verilog/
229 case changed to casex. mohor 6612d 08h /ethmac/tags/rel_17/rtl/verilog/
227 Changed BIST scan signals. tadejm 6612d 12h /ethmac/tags/rel_17/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6612d 13h /ethmac/tags/rel_17/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6616d 13h /ethmac/tags/rel_17/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6619d 13h /ethmac/tags/rel_17/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 6619d 15h /ethmac/tags/rel_17/rtl/verilog/
214 Signals for WISHBONE B3 compliant interface added. mohor 6620d 12h /ethmac/tags/rel_17/rtl/verilog/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6620d 12h /ethmac/tags/rel_17/rtl/verilog/

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