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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

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67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8076d 17h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 8077d 19h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8078d 10h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
46 HASH0 and HASH1 registers added. mohor 8080d 13h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
42 Rx status is written back to the BD. mohor 8084d 14h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 8087d 13h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
37 Link in the header changed. mohor 8100d 20h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8149d 15h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8149d 20h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v
29 Generic memory model is used. Defines are changed for the same reason. mohor 8171d 16h /ethmac/tags/rel_17/rtl/verilog/eth_defines.v

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