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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_random.v] - Rev 338


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Rev Log message Author Age Path
338 root 4467d 16h /ethmac/tags/rel_17/rtl/verilog/eth_random.v
335 New directory structure. root 4524d 22h /ethmac/tags/rel_17/rtl/verilog/eth_random.v
287 This commit was manufactured by cvs2svn to create tag 'rel_17'. 6620d 20h /ethmac/tags/rel_17/rtl/verilog/eth_random.v
285 Binary operator used instead of unary (xnor). mohor 6620d 20h /ethmac/tags/rel_17/rtl/verilog/eth_random.v
37 Link in the header changed. mohor 7126d 21h /ethmac/tags/rel_17/rtl/verilog/eth_random.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7222d 23h /ethmac/tags/rel_17/rtl/verilog/eth_random.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7296d 17h /ethmac/tags/rel_17/rtl/verilog/eth_random.v

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