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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_registers.v] - Rev 338

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46 HASH0 and HASH1 registers added. mohor 8080d 00h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8100d 06h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8149d 02h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8149d 06h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8196d 08h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8197d 05h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8221d 02h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8270d 02h /ethmac/tags/rel_17/rtl/verilog/eth_registers.v

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