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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Rev 168

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Rev Log message Author Age Path
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7889d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7891d 18h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7892d 16h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7897d 10h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7938d 11h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7946d 10h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8021d 19h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8032d 15h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8060d 15h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8087d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8087d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
70 Small fixes. mohor 8095d 18h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8097d 15h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8097d 16h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8097d 22h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8098d 15h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8098d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8099d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8101d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
43 Tx status is written back to the BD. mohor 8102d 20h /ethmac/tags/rel_17/rtl/verilog/eth_top.v

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