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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Rev 244

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244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7827d 04h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7828d 00h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7854d 05h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7861d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7862d 05h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
210 BIST added. mohor 7862d 06h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7882d 05h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7890d 07h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7892d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7893d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7898d 04h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7939d 04h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7947d 03h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8022d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8033d 08h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8061d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8088d 05h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8088d 06h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
70 Small fixes. mohor 8096d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8098d 08h /ethmac/tags/rel_17/rtl/verilog/eth_top.v

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