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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Rev 338

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338 root 4156d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
335 New directory structure. root 4213d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
287 This commit was manufactured by cvs2svn to create tag 'rel_17'. 6309d 16h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 6443d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 6451d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6452d 15h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6513d 02h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 6514d 03h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6515d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6515d 10h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
248 wb_rst_i is used for MIIM reset. mohor 6516d 10h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6520d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6521d 05h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 6547d 10h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 6554d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 6555d 11h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
210 BIST added. mohor 6555d 11h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6575d 10h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 6583d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 6585d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 6586d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 6591d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6632d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6640d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6715d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6726d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 6754d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 6781d 11h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 6781d 11h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
70 Small fixes. mohor 6789d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v

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