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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Rev 338

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Rev Log message Author Age Path
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 6586d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 6591d 08h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6632d 09h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6640d 08h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6715d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6726d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 6754d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 6781d 10h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 6781d 11h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
70 Small fixes. mohor 6789d 16h /ethmac/tags/rel_17/rtl/verilog/eth_top.v

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