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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6454d 19h /ethmac/tags/rel_18/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6454d 19h /ethmac/tags/rel_18/
238 Defines fixed to use generic RAM by default. mohor 6466d 23h /ethmac/tags/rel_18/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6469d 05h /ethmac/tags/rel_18/
235 rev 4. mohor 6469d 19h /ethmac/tags/rel_18/
234 Figure list assed to the revision 3. mohor 6470d 03h /ethmac/tags/rel_18/
233 Revision 0.3 released. Some figures added. mohor 6470d 04h /ethmac/tags/rel_18/
232 fpga define added. mohor 6474d 23h /ethmac/tags/rel_18/
231 Description of Core Modules added (figure). mohor 6477d 00h /ethmac/tags/rel_18/
229 case changed to casex. mohor 6480d 21h /ethmac/tags/rel_18/
227 Changed BIST scan signals. tadejm 6481d 01h /ethmac/tags/rel_18/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6481d 02h /ethmac/tags/rel_18/
225 Some minor changes. tadejm 6481d 02h /ethmac/tags/rel_18/
224 Signals for a wave window in Modelsim. tadejm 6481d 03h /ethmac/tags/rel_18/
223 Some code changed due to bug fixes. tadejm 6481d 04h /ethmac/tags/rel_18/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6485d 02h /ethmac/tags/rel_18/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6488d 02h /ethmac/tags/rel_18/
218 Typo error fixed. (When using Bist) mohor 6488d 04h /ethmac/tags/rel_18/
217 Bist supported. mohor 6488d 04h /ethmac/tags/rel_18/
216 Bist signals added. mohor 6488d 04h /ethmac/tags/rel_18/

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