OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_18/] [bench/] [verilog/] - Rev 350

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 5461d 09h /ethmac/tags/rel_18/bench/verilog/
335 New directory structure. root 5518d 14h /ethmac/tags/rel_18/bench/verilog/
289 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7588d 10h /ethmac/tags/rel_18/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7614d 13h /ethmac/tags/rel_18/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7747d 08h /ethmac/tags/rel_18/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7748d 11h /ethmac/tags/rel_18/bench/verilog/
274 Backup version. Not fully working. tadejm 7756d 05h /ethmac/tags/rel_18/bench/verilog/
267 Full duplex control frames tested. mohor 7812d 08h /ethmac/tags/rel_18/bench/verilog/
266 Flow control test almost finished. mohor 7817d 07h /ethmac/tags/rel_18/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7817d 22h /ethmac/tags/rel_18/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7818d 10h /ethmac/tags/rel_18/bench/verilog/
254 Temp version. mohor 7820d 04h /ethmac/tags/rel_18/bench/verilog/
252 Just some updates. tadejm 7820d 07h /ethmac/tags/rel_18/bench/verilog/
243 Late collision is not reported any more. tadejm 7825d 11h /ethmac/tags/rel_18/bench/verilog/
227 Changed BIST scan signals. tadejm 7852d 07h /ethmac/tags/rel_18/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7852d 10h /ethmac/tags/rel_18/bench/verilog/
216 Bist signals added. mohor 7859d 11h /ethmac/tags/rel_18/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7861d 11h /ethmac/tags/rel_18/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7880d 10h /ethmac/tags/rel_18/bench/verilog/
192 Some additional reports added tadej 7882d 06h /ethmac/tags/rel_18/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.