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Rev Log message Author Age Path
252 Just some updates. tadejm 7124d 15h /ethmac/tags/rel_19/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7124d 15h /ethmac/tags/rel_19/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7124d 15h /ethmac/tags/rel_19/
248 wb_rst_i is used for MIIM reset. mohor 7125d 15h /ethmac/tags/rel_19/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7128d 18h /ethmac/tags/rel_19/
245 Rev 1.7. mohor 7129d 12h /ethmac/tags/rel_19/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7129d 14h /ethmac/tags/rel_19/
243 Late collision is not reported any more. tadejm 7129d 19h /ethmac/tags/rel_19/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7130d 10h /ethmac/tags/rel_19/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7130d 10h /ethmac/tags/rel_19/

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