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[/] [ethmac/] [tags/] [rel_19/] [bench/] [verilog/] - Rev 365

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Rev Log message Author Age Path
338 root 5461d 22h /ethmac/tags/rel_19/bench/verilog/
335 New directory structure. root 5519d 04h /ethmac/tags/rel_19/bench/verilog/
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7554d 00h /ethmac/tags/rel_19/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7615d 02h /ethmac/tags/rel_19/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7747d 22h /ethmac/tags/rel_19/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7749d 00h /ethmac/tags/rel_19/bench/verilog/
274 Backup version. Not fully working. tadejm 7756d 18h /ethmac/tags/rel_19/bench/verilog/
267 Full duplex control frames tested. mohor 7812d 21h /ethmac/tags/rel_19/bench/verilog/
266 Flow control test almost finished. mohor 7817d 20h /ethmac/tags/rel_19/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7818d 12h /ethmac/tags/rel_19/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7819d 00h /ethmac/tags/rel_19/bench/verilog/
254 Temp version. mohor 7820d 17h /ethmac/tags/rel_19/bench/verilog/
252 Just some updates. tadejm 7820d 20h /ethmac/tags/rel_19/bench/verilog/
243 Late collision is not reported any more. tadejm 7826d 01h /ethmac/tags/rel_19/bench/verilog/
227 Changed BIST scan signals. tadejm 7852d 21h /ethmac/tags/rel_19/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7853d 00h /ethmac/tags/rel_19/bench/verilog/
216 Bist signals added. mohor 7860d 00h /ethmac/tags/rel_19/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7862d 00h /ethmac/tags/rel_19/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7880d 23h /ethmac/tags/rel_19/bench/verilog/
192 Some additional reports added tadej 7882d 20h /ethmac/tags/rel_19/bench/verilog/

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