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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

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338 root 5441d 06h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
335 New directory structure. root 5498d 11h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7533d 07h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7594d 09h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7800d 03h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7804d 07h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 7818d 03h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
232 fpga define added. mohor 7826d 02h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7840d 04h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
211 Bist added. mohor 7840d 05h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7857d 03h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7876d 02h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 7894d 23h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7897d 02h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7919d 06h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8000d 11h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8009d 12h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8045d 08h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 8066d 05h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 8076d 07h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8076d 08h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 8077d 10h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8078d 01h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
46 HASH0 and HASH1 registers added. mohor 8080d 04h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
42 Rx status is written back to the BD. mohor 8084d 05h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 8087d 04h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
37 Link in the header changed. mohor 8100d 11h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8149d 06h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8149d 11h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
29 Generic memory model is used. Defines are changed for the same reason. mohor 8171d 07h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v

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