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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_registers.v] - Rev 338

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338 root 5442d 00h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
335 New directory structure. root 5499d 05h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7534d 01h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7650d 22h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7798d 13h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7800d 21h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7805d 20h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
164 Ethernet debug registers removed. mohor 7871d 04h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7876d 20h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 7892d 23h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 7895d 16h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7895d 16h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7895d 17h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7897d 20h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8012d 01h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8066d 23h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8076d 01h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8077d 01h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8078d 04h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8078d 19h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8080d 22h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8101d 04h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8150d 00h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8150d 04h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8197d 06h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8198d 03h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8222d 00h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8271d 00h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v

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