Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_txstatem.v] - Rev 338


Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 4112d 14h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
335 New directory structure. root 4169d 20h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 6204d 16h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
276 Defer indication changed. tadejm 6399d 16h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6491d 17h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
37 Link in the header changed. mohor 6771d 19h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6867d 21h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
18 Few little NCSIM warnings fixed. mohor 6905d 15h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 6941d 15h /ethmac/tags/rel_19/rtl/verilog/eth_txstatem.v

powered by: WebSVN 2.1.0

© copyright 1999-2020, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.