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[/] [ethmac/] [tags/] [rel_2/] - Rev 110

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Rev Log message Author Age Path
110 m_wb_cyc_o signal released after every single transfer. mohor 6284d 01h /ethmac/tags/rel_2/
109 Comment removed. mohor 6284d 02h /ethmac/tags/rel_2/
108 Testbench supports unaligned accesses. mohor 6351d 12h /ethmac/tags/rel_2/
107 TX_BUF_BASE changed. mohor 6351d 12h /ethmac/tags/rel_2/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6351d 12h /ethmac/tags/rel_2/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6360d 13h /ethmac/tags/rel_2/
104 FCS should not be included in NibbleMinFl. mohor 6362d 07h /ethmac/tags/rel_2/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6362d 08h /ethmac/tags/rel_2/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6362d 08h /ethmac/tags/rel_2/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6362d 08h /ethmac/tags/rel_2/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6362d 08h /ethmac/tags/rel_2/
99 Document revised. mohor 6369d 07h /ethmac/tags/rel_2/
98 Document revised. mohor 6369d 07h /ethmac/tags/rel_2/
97 Small typo fixed. lampret 6386d 06h /ethmac/tags/rel_2/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 6390d 06h /ethmac/tags/rel_2/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 6390d 09h /ethmac/tags/rel_2/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 6390d 09h /ethmac/tags/rel_2/
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 6395d 07h /ethmac/tags/rel_2/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6396d 09h /ethmac/tags/rel_2/
91 Comments in Slovene language removed. mohor 6396d 09h /ethmac/tags/rel_2/
90 casex changed with case, fifo reset changed. mohor 6396d 09h /ethmac/tags/rel_2/
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.
mohor 6400d 07h /ethmac/tags/rel_2/
88 rx_fifo was not always cleared ok. Fixed. mohor 6406d 06h /ethmac/tags/rel_2/
87 Status was not latched correctly sometimes. Fixed. mohor 6406d 08h /ethmac/tags/rel_2/
86 Big Endian problem when sending frames fixed. mohor 6407d 15h /ethmac/tags/rel_2/
85 Log info was missing. mohor 6413d 01h /ethmac/tags/rel_2/
84 LinkFail signal was not latching appropriate bit. mohor 6413d 01h /ethmac/tags/rel_2/
83 MAC address recognition was not correct (bytes swaped). mohor 6413d 01h /ethmac/tags/rel_2/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 6413d 03h /ethmac/tags/rel_2/
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 6413d 03h /ethmac/tags/rel_2/

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