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Rev Log message Author Age Path
338 root 3728d 11h /ethmac/tags/rel_2/
335 New directory structure. root 3785d 16h /ethmac/tags/rel_2/
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 6204d 08h /ethmac/tags/rel_2/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6204d 08h /ethmac/tags/rel_2/
126 InvalidSymbol generation changed. mohor 6204d 08h /ethmac/tags/rel_2/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 6204d 08h /ethmac/tags/rel_2/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6204d 09h /ethmac/tags/rel_2/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6206d 10h /ethmac/tags/rel_2/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6206d 10h /ethmac/tags/rel_2/
120 Unused files removed. mohor 6206d 11h /ethmac/tags/rel_2/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6206d 11h /ethmac/tags/rel_2/
118 ShiftEnded synchronization changed. mohor 6210d 01h /ethmac/tags/rel_2/
117 Clock mrx_clk set to 2.5 MHz. mohor 6210d 12h /ethmac/tags/rel_2/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6210d 12h /ethmac/tags/rel_2/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6211d 10h /ethmac/tags/rel_2/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6212d 07h /ethmac/tags/rel_2/
113 RxPointer bug fixed. mohor 6218d 23h /ethmac/tags/rel_2/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6219d 13h /ethmac/tags/rel_2/
111 Master state machine had a bug when switching from master write to
master read.
mohor 6220d 02h /ethmac/tags/rel_2/
110 m_wb_cyc_o signal released after every single transfer. mohor 6220d 05h /ethmac/tags/rel_2/
109 Comment removed. mohor 6220d 06h /ethmac/tags/rel_2/
108 Testbench supports unaligned accesses. mohor 6287d 16h /ethmac/tags/rel_2/
107 TX_BUF_BASE changed. mohor 6287d 16h /ethmac/tags/rel_2/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6287d 16h /ethmac/tags/rel_2/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6296d 17h /ethmac/tags/rel_2/
104 FCS should not be included in NibbleMinFl. mohor 6298d 11h /ethmac/tags/rel_2/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6298d 12h /ethmac/tags/rel_2/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6298d 12h /ethmac/tags/rel_2/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6298d 12h /ethmac/tags/rel_2/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6298d 12h /ethmac/tags/rel_2/

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