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[/] [ethmac/] [tags/] [rel_2/] [rtl/] - Rev 106

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Rev Log message Author Age Path
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7459d 00h /ethmac/tags/rel_2/rtl/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7468d 01h /ethmac/tags/rel_2/rtl/
104 FCS should not be included in NibbleMinFl. mohor 7469d 19h /ethmac/tags/rel_2/rtl/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7469d 20h /ethmac/tags/rel_2/rtl/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7469d 20h /ethmac/tags/rel_2/rtl/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7469d 20h /ethmac/tags/rel_2/rtl/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7469d 20h /ethmac/tags/rel_2/rtl/
97 Small typo fixed. lampret 7493d 18h /ethmac/tags/rel_2/rtl/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 7497d 18h /ethmac/tags/rel_2/rtl/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7497d 20h /ethmac/tags/rel_2/rtl/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7497d 20h /ethmac/tags/rel_2/rtl/
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 7502d 19h /ethmac/tags/rel_2/rtl/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 7503d 21h /ethmac/tags/rel_2/rtl/
91 Comments in Slovene language removed. mohor 7503d 21h /ethmac/tags/rel_2/rtl/
90 casex changed with case, fifo reset changed. mohor 7503d 21h /ethmac/tags/rel_2/rtl/
88 rx_fifo was not always cleared ok. Fixed. mohor 7513d 18h /ethmac/tags/rel_2/rtl/
87 Status was not latched correctly sometimes. Fixed. mohor 7513d 20h /ethmac/tags/rel_2/rtl/
86 Big Endian problem when sending frames fixed. mohor 7515d 03h /ethmac/tags/rel_2/rtl/
85 Log info was missing. mohor 7520d 13h /ethmac/tags/rel_2/rtl/
84 LinkFail signal was not latching appropriate bit. mohor 7520d 13h /ethmac/tags/rel_2/rtl/
83 MAC address recognition was not correct (bytes swaped). mohor 7520d 13h /ethmac/tags/rel_2/rtl/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 7520d 15h /ethmac/tags/rel_2/rtl/
80 Small fixes for external/internal DMA missmatches. mohor 7524d 17h /ethmac/tags/rel_2/rtl/
79 RetryCntLatched was unused and removed from design mohor 7524d 17h /ethmac/tags/rel_2/rtl/
78 WB_SEL_I was unused and removed from design mohor 7524d 17h /ethmac/tags/rel_2/rtl/
77 Interrupts changed mohor 7524d 17h /ethmac/tags/rel_2/rtl/
76 Interrupts changed in the top file mohor 7524d 17h /ethmac/tags/rel_2/rtl/
75 r_Bro is used for accepting/denying frames mohor 7524d 17h /ethmac/tags/rel_2/rtl/
74 Reset values are passed to registers through parameters mohor 7524d 18h /ethmac/tags/rel_2/rtl/
73 Number of interrupts changed mohor 7524d 18h /ethmac/tags/rel_2/rtl/

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