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[/] [ethmac/] [tags/] [rel_2/] [rtl/] - Rev 358

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Rev Log message Author Age Path
338 root 5468d 19h /ethmac/tags/rel_2/rtl
335 New directory structure. root 5526d 00h /ethmac/tags/rel_2/rtl
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7944d 15h /ethmac/tags/rel_2/rtl
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7944d 15h /ethmac/tags/rel_2/rtl
126 InvalidSymbol generation changed. mohor 7944d 16h /ethmac/tags/rel_2/rtl
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7944d 16h /ethmac/tags/rel_2/rtl
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7946d 17h /ethmac/tags/rel_2/rtl
120 Unused files removed. mohor 7946d 18h /ethmac/tags/rel_2/rtl
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7946d 18h /ethmac/tags/rel_2/rtl
118 ShiftEnded synchronization changed. mohor 7950d 09h /ethmac/tags/rel_2/rtl
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7951d 18h /ethmac/tags/rel_2/rtl
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7952d 15h /ethmac/tags/rel_2/rtl
113 RxPointer bug fixed. mohor 7959d 07h /ethmac/tags/rel_2/rtl
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7959d 21h /ethmac/tags/rel_2/rtl
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7960d 10h /ethmac/tags/rel_2/rtl
110 m_wb_cyc_o signal released after every single transfer. mohor 7960d 13h /ethmac/tags/rel_2/rtl
109 Comment removed. mohor 7960d 14h /ethmac/tags/rel_2/rtl
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8028d 00h /ethmac/tags/rel_2/rtl
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8037d 01h /ethmac/tags/rel_2/rtl
104 FCS should not be included in NibbleMinFl. mohor 8038d 19h /ethmac/tags/rel_2/rtl

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