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[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] - Rev 365

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Rev Log message Author Age Path
338 root 5459d 14h /ethmac/tags/rel_2/rtl/verilog/
335 New directory structure. root 5516d 19h /ethmac/tags/rel_2/rtl/verilog/
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7935d 11h /ethmac/tags/rel_2/rtl/verilog/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7935d 11h /ethmac/tags/rel_2/rtl/verilog/
126 InvalidSymbol generation changed. mohor 7935d 11h /ethmac/tags/rel_2/rtl/verilog/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7935d 11h /ethmac/tags/rel_2/rtl/verilog/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7937d 13h /ethmac/tags/rel_2/rtl/verilog/
120 Unused files removed. mohor 7937d 14h /ethmac/tags/rel_2/rtl/verilog/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7937d 14h /ethmac/tags/rel_2/rtl/verilog/
118 ShiftEnded synchronization changed. mohor 7941d 05h /ethmac/tags/rel_2/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7942d 13h /ethmac/tags/rel_2/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7943d 10h /ethmac/tags/rel_2/rtl/verilog/
113 RxPointer bug fixed. mohor 7950d 02h /ethmac/tags/rel_2/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7950d 16h /ethmac/tags/rel_2/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7951d 05h /ethmac/tags/rel_2/rtl/verilog/
110 m_wb_cyc_o signal released after every single transfer. mohor 7951d 08h /ethmac/tags/rel_2/rtl/verilog/
109 Comment removed. mohor 7951d 09h /ethmac/tags/rel_2/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8018d 19h /ethmac/tags/rel_2/rtl/verilog/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8027d 20h /ethmac/tags/rel_2/rtl/verilog/
104 FCS should not be included in NibbleMinFl. mohor 8029d 14h /ethmac/tags/rel_2/rtl/verilog/

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