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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7451d 21h /ethmac/tags/rel_20/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7454d 02h /ethmac/tags/rel_20/
235 rev 4. mohor 7454d 17h /ethmac/tags/rel_20/
234 Figure list assed to the revision 3. mohor 7455d 01h /ethmac/tags/rel_20/
233 Revision 0.3 released. Some figures added. mohor 7455d 01h /ethmac/tags/rel_20/
232 fpga define added. mohor 7459d 20h /ethmac/tags/rel_20/
231 Description of Core Modules added (figure). mohor 7461d 21h /ethmac/tags/rel_20/
229 case changed to casex. mohor 7465d 18h /ethmac/tags/rel_20/
227 Changed BIST scan signals. tadejm 7465d 22h /ethmac/tags/rel_20/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7465d 23h /ethmac/tags/rel_20/
225 Some minor changes. tadejm 7465d 23h /ethmac/tags/rel_20/
224 Signals for a wave window in Modelsim. tadejm 7466d 01h /ethmac/tags/rel_20/
223 Some code changed due to bug fixes. tadejm 7466d 01h /ethmac/tags/rel_20/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7469d 23h /ethmac/tags/rel_20/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7472d 23h /ethmac/tags/rel_20/
218 Typo error fixed. (When using Bist) mohor 7473d 01h /ethmac/tags/rel_20/
217 Bist supported. mohor 7473d 01h /ethmac/tags/rel_20/
216 Bist signals added. mohor 7473d 01h /ethmac/tags/rel_20/
215 Bist supported. mohor 7473d 02h /ethmac/tags/rel_20/
214 Signals for WISHBONE B3 compliant interface added. mohor 7473d 22h /ethmac/tags/rel_20/

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