OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] - Rev 266

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
266 Flow control test almost finished. mohor 7824d 12h /ethmac/tags/rel_20
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7824d 16h /ethmac/tags/rel_20
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7825d 04h /ethmac/tags/rel_20
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.		 mohor 7825d 04h /ethmac/tags/rel_20
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7825d 04h /ethmac/tags/rel_20
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7825d 16h /ethmac/tags/rel_20
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7826d 05h /ethmac/tags/rel_20
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7826d 06h /ethmac/tags/rel_20
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7826d 06h /ethmac/tags/rel_20
255 TPauseRq synchronized to tx_clk. mohor 7826d 06h /ethmac/tags/rel_20
254 Temp version. mohor 7827d 09h /ethmac/tags/rel_20
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7827d 12h /ethmac/tags/rel_20
252 Just some updates. tadejm 7827d 12h /ethmac/tags/rel_20
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7827d 12h /ethmac/tags/rel_20
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7827d 12h /ethmac/tags/rel_20
248 wb_rst_i is used for MIIM reset. mohor 7828d 12h /ethmac/tags/rel_20
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7831d 15h /ethmac/tags/rel_20
245 Rev 1.7. mohor 7832d 09h /ethmac/tags/rel_20
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7832d 11h /ethmac/tags/rel_20
243 Late collision is not reported any more. tadejm 7832d 17h /ethmac/tags/rel_20

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.