OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] - Rev 31

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 6897d 15h /ethmac/tags/rel_20/
30 BD section updated. mohor 6899d 11h /ethmac/tags/rel_20/
29 Generic memory model is used. Defines are changed for the same reason. mohor 6919d 10h /ethmac/tags/rel_20/
28 New release. Name changed to lower case. mohor 6922d 02h /ethmac/tags/rel_20/
27 File names changed to lower case. mohor 6922d 02h /ethmac/tags/rel_20/
26 First release of product brief. mohor 6922d 02h /ethmac/tags/rel_20/
25 First release of product brief. mohor 6922d 02h /ethmac/tags/rel_20/
24 Log file added. mohor 6944d 13h /ethmac/tags/rel_20/
23 Number of addresses (wb_adr_i) minimized. mohor 6944d 13h /ethmac/tags/rel_20/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6944d 16h /ethmac/tags/rel_20/
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 6945d 12h /ethmac/tags/rel_20/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6969d 10h /ethmac/tags/rel_20/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6969d 10h /ethmac/tags/rel_20/
18 Few little NCSIM warnings fixed. mohor 6982d 10h /ethmac/tags/rel_20/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 7009d 11h /ethmac/tags/rel_20/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 7016d 16h /ethmac/tags/rel_20/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7018d 10h /ethmac/tags/rel_20/
14 Unconnected signals are now connected. mohor 7022d 15h /ethmac/tags/rel_20/
13 New directory structure. Files upodated and put together. mohor 7025d 00h /ethmac/tags/rel_20/
12 Directory structure changed. Files checked and joind together. mohor 7025d 03h /ethmac/tags/rel_20/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.