URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [rtl/] - Rev 244

Rev	Log message	Author	Age	Path
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7884d 12h	/ethmac/tags/rel_20/rtl/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7887d 13h	/ethmac/tags/rel_20/rtl/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7895d 15h	/ethmac/tags/rel_20/rtl/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7896d 16h	/ethmac/tags/rel_20/rtl/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7897d 16h	/ethmac/tags/rel_20/rtl/
165	HASH improvement needed.	mohor	7897d 19h	/ethmac/tags/rel_20/rtl/
164	Ethernet debug registers removed.	mohor	7897d 20h	/ethmac/tags/rel_20/rtl/
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7898d 17h	/ethmac/tags/rel_20/rtl/
160	error acknowledge cycle termination added to display.	mohor	7898d 17h	/ethmac/tags/rel_20/rtl/
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7899d 14h	/ethmac/tags/rel_20/rtl/