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[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 259

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7835d 16h /ethmac/tags/rel_20/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7838d 17h /ethmac/tags/rel_20/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 7838d 19h /ethmac/tags/rel_20/rtl/verilog/
214 Signals for WISHBONE B3 compliant interface added. mohor 7839d 16h /ethmac/tags/rel_20/rtl/verilog/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7839d 16h /ethmac/tags/rel_20/rtl/verilog/
212 Minor $display change. mohor 7839d 16h /ethmac/tags/rel_20/rtl/verilog/
211 Bist added. mohor 7839d 16h /ethmac/tags/rel_20/rtl/verilog/
210 BIST added. mohor 7839d 16h /ethmac/tags/rel_20/rtl/verilog/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7856d 14h /ethmac/tags/rel_20/rtl/verilog/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7856d 14h /ethmac/tags/rel_20/rtl/verilog/

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