OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 275

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
275 Fix MTxErr or prevent sending too big frames. mohor 7735d 00h /ethmac/tags/rel_20/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7735d 20h /ethmac/tags/rel_20/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7736d 21h /ethmac/tags/rel_20/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7737d 21h /ethmac/tags/rel_20/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7796d 20h /ethmac/tags/rel_20/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7797d 07h /ethmac/tags/rel_20/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7798d 09h /ethmac/tags/rel_20/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7798d 09h /ethmac/tags/rel_20/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7798d 09h /ethmac/tags/rel_20/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 7798d 09h /ethmac/tags/rel_20/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7799d 15h /ethmac/tags/rel_20/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7799d 16h /ethmac/tags/rel_20/rtl/verilog/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7799d 16h /ethmac/tags/rel_20/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 7800d 16h /ethmac/tags/rel_20/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7803d 19h /ethmac/tags/rel_20/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7804d 15h /ethmac/tags/rel_20/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7805d 11h /ethmac/tags/rel_20/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7805d 11h /ethmac/tags/rel_20/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7805d 11h /ethmac/tags/rel_20/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7805d 11h /ethmac/tags/rel_20/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.