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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7334d 09h /ethmac/tags/rel_21/
235 rev 4. mohor 7335d 00h /ethmac/tags/rel_21/
234 Figure list assed to the revision 3. mohor 7335d 08h /ethmac/tags/rel_21/
233 Revision 0.3 released. Some figures added. mohor 7335d 09h /ethmac/tags/rel_21/
232 fpga define added. mohor 7340d 04h /ethmac/tags/rel_21/
231 Description of Core Modules added (figure). mohor 7342d 05h /ethmac/tags/rel_21/
229 case changed to casex. mohor 7346d 01h /ethmac/tags/rel_21/
227 Changed BIST scan signals. tadejm 7346d 05h /ethmac/tags/rel_21/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7346d 07h /ethmac/tags/rel_21/
225 Some minor changes. tadejm 7346d 07h /ethmac/tags/rel_21/
224 Signals for a wave window in Modelsim. tadejm 7346d 08h /ethmac/tags/rel_21/
223 Some code changed due to bug fixes. tadejm 7346d 08h /ethmac/tags/rel_21/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7350d 06h /ethmac/tags/rel_21/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7353d 07h /ethmac/tags/rel_21/
218 Typo error fixed. (When using Bist) mohor 7353d 09h /ethmac/tags/rel_21/
217 Bist supported. mohor 7353d 09h /ethmac/tags/rel_21/
216 Bist signals added. mohor 7353d 09h /ethmac/tags/rel_21/
215 Bist supported. mohor 7353d 10h /ethmac/tags/rel_21/
214 Signals for WISHBONE B3 compliant interface added. mohor 7354d 06h /ethmac/tags/rel_21/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7354d 06h /ethmac/tags/rel_21/

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