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Rev Log message Author Age Path
225 Some minor changes. tadejm 8089d 17h /ethmac/tags/rel_21
224 Signals for a wave window in Modelsim. tadejm 8089d 19h /ethmac/tags/rel_21
223 Some code changed due to bug fixes. tadejm 8089d 19h /ethmac/tags/rel_21
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 8093d 17h /ethmac/tags/rel_21
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 8096d 17h /ethmac/tags/rel_21
218 Typo error fixed. (When using Bist) mohor 8096d 19h /ethmac/tags/rel_21
217 Bist supported. mohor 8096d 19h /ethmac/tags/rel_21
216 Bist signals added. mohor 8096d 20h /ethmac/tags/rel_21
215 Bist supported. mohor 8096d 20h /ethmac/tags/rel_21
214 Signals for WISHBONE B3 compliant interface added. mohor 8097d 16h /ethmac/tags/rel_21
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 8097d 16h /ethmac/tags/rel_21
212 Minor $display change. mohor 8097d 16h /ethmac/tags/rel_21
211 Bist added. mohor 8097d 16h /ethmac/tags/rel_21
210 BIST added. mohor 8097d 17h /ethmac/tags/rel_21
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 8098d 20h /ethmac/tags/rel_21
208 Virtual Silicon RAMs moved to lib directory tadej 8114d 14h /ethmac/tags/rel_21
207 Virtual Silicon RAM support fixed tadej 8114d 14h /ethmac/tags/rel_21
206 Virtual Silicon RAM added to the simulation. mohor 8114d 14h /ethmac/tags/rel_21
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 8114d 15h /ethmac/tags/rel_21
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8114d 15h /ethmac/tags/rel_21

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