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[/] [ethmac/] [tags/] [rel_21] - Rev 240

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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7832d 22h /ethmac/tags/rel_21
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7832d 22h /ethmac/tags/rel_21
238 Defines fixed to use generic RAM by default. mohor 7845d 02h /ethmac/tags/rel_21
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7847d 08h /ethmac/tags/rel_21
235 rev 4. mohor 7847d 22h /ethmac/tags/rel_21
234 Figure list assed to the revision 3. mohor 7848d 07h /ethmac/tags/rel_21
233 Revision 0.3 released. Some figures added. mohor 7848d 07h /ethmac/tags/rel_21
232 fpga define added. mohor 7853d 02h /ethmac/tags/rel_21
231 Description of Core Modules added (figure). mohor 7855d 03h /ethmac/tags/rel_21
229 case changed to casex. mohor 7859d 00h /ethmac/tags/rel_21
227 Changed BIST scan signals. tadejm 7859d 04h /ethmac/tags/rel_21
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7859d 05h /ethmac/tags/rel_21
225 Some minor changes. tadejm 7859d 05h /ethmac/tags/rel_21
224 Signals for a wave window in Modelsim. tadejm 7859d 07h /ethmac/tags/rel_21
223 Some code changed due to bug fixes. tadejm 7859d 07h /ethmac/tags/rel_21
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7863d 05h /ethmac/tags/rel_21
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7866d 05h /ethmac/tags/rel_21
218 Typo error fixed. (When using Bist) mohor 7866d 07h /ethmac/tags/rel_21
217 Bist supported. mohor 7866d 07h /ethmac/tags/rel_21
216 Bist signals added. mohor 7866d 07h /ethmac/tags/rel_21
215 Bist supported. mohor 7866d 08h /ethmac/tags/rel_21
214 Signals for WISHBONE B3 compliant interface added. mohor 7867d 04h /ethmac/tags/rel_21
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7867d 04h /ethmac/tags/rel_21
212 Minor $display change. mohor 7867d 04h /ethmac/tags/rel_21
211 Bist added. mohor 7867d 04h /ethmac/tags/rel_21
210 BIST added. mohor 7867d 04h /ethmac/tags/rel_21
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7868d 07h /ethmac/tags/rel_21
208 Virtual Silicon RAMs moved to lib directory tadej 7884d 01h /ethmac/tags/rel_21
207 Virtual Silicon RAM support fixed tadej 7884d 02h /ethmac/tags/rel_21
206 Virtual Silicon RAM added to the simulation. mohor 7884d 02h /ethmac/tags/rel_21

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