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Rev Log message Author Age Path
141 Syntax error fixed. mohor 7600d 23h /ethmac/tags/rel_22/
140 Syntax error fixed. mohor 7600d 23h /ethmac/tags/rel_22/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7600d 23h /ethmac/tags/rel_22/
138 Synchronous reset added. mohor 7600d 23h /ethmac/tags/rel_22/
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 7600d 23h /ethmac/tags/rel_22/
136 Parameter ResetValue changed to capital letters. mohor 7601d 09h /ethmac/tags/rel_22/
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 7603d 01h /ethmac/tags/rel_22/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7603d 02h /ethmac/tags/rel_22/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7603d 03h /ethmac/tags/rel_22/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7603d 03h /ethmac/tags/rel_22/
131 LinkFail signal was not latching appropriate bit. mohor 7603d 03h /ethmac/tags/rel_22/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 7603d 03h /ethmac/tags/rel_22/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7603d 04h /ethmac/tags/rel_22/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7623d 03h /ethmac/tags/rel_22/
126 InvalidSymbol generation changed. mohor 7623d 03h /ethmac/tags/rel_22/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 7623d 03h /ethmac/tags/rel_22/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7623d 04h /ethmac/tags/rel_22/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7625d 05h /ethmac/tags/rel_22/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7625d 05h /ethmac/tags/rel_22/
120 Unused files removed. mohor 7625d 06h /ethmac/tags/rel_22/

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