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Rev Log message Author Age Path
84 LinkFail signal was not latching appropriate bit. mohor 8082d 23h /ethmac/tags/rel_23/
83 MAC address recognition was not correct (bytes swaped). mohor 8082d 23h /ethmac/tags/rel_23/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8083d 01h /ethmac/tags/rel_23/
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8083d 01h /ethmac/tags/rel_23/
80 Small fixes for external/internal DMA missmatches. mohor 8087d 03h /ethmac/tags/rel_23/
79 RetryCntLatched was unused and removed from design mohor 8087d 03h /ethmac/tags/rel_23/
78 WB_SEL_I was unused and removed from design mohor 8087d 04h /ethmac/tags/rel_23/
77 Interrupts changed mohor 8087d 04h /ethmac/tags/rel_23/
76 Interrupts changed in the top file mohor 8087d 04h /ethmac/tags/rel_23/
75 r_Bro is used for accepting/denying frames mohor 8087d 04h /ethmac/tags/rel_23/
74 Reset values are passed to registers through parameters mohor 8087d 04h /ethmac/tags/rel_23/
73 Number of interrupts changed mohor 8087d 04h /ethmac/tags/rel_23/
72 Retry is not activated when a Tx Underrun occured mohor 8091d 07h /ethmac/tags/rel_23/
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.		 mohor 8095d 08h /ethmac/tags/rel_23/
70 Small fixes. mohor 8095d 09h /ethmac/tags/rel_23/
69 Define missmatch fixed. mohor 8096d 06h /ethmac/tags/rel_23/
68 Registered trimmed. Unused registers removed. mohor 8097d 06h /ethmac/tags/rel_23/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8097d 07h /ethmac/tags/rel_23/
66 Testbench fixed, code simplified, unused signals removed. mohor 8097d 13h /ethmac/tags/rel_23/
65 Testbench fixed, code simplified, unused signals removed. mohor 8097d 13h /ethmac/tags/rel_23/

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