OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_23/] [rtl/] - Rev 146

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7876d 00h /ethmac/tags/rel_23/rtl/
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7876d 00h /ethmac/tags/rel_23/rtl/
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 7892d 03h /ethmac/tags/rel_23/rtl/
141 Syntax error fixed. mohor 7894d 20h /ethmac/tags/rel_23/rtl/
140 Syntax error fixed. mohor 7894d 20h /ethmac/tags/rel_23/rtl/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7894d 21h /ethmac/tags/rel_23/rtl/
138 Synchronous reset added. mohor 7894d 21h /ethmac/tags/rel_23/rtl/
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 7894d 21h /ethmac/tags/rel_23/rtl/
136 Parameter ResetValue changed to capital letters. mohor 7895d 06h /ethmac/tags/rel_23/rtl/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7896d 23h /ethmac/tags/rel_23/rtl/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7897d 00h /ethmac/tags/rel_23/rtl/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7897d 00h /ethmac/tags/rel_23/rtl/
131 LinkFail signal was not latching appropriate bit. mohor 7897d 01h /ethmac/tags/rel_23/rtl/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7897d 02h /ethmac/tags/rel_23/rtl/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7917d 00h /ethmac/tags/rel_23/rtl/
126 InvalidSymbol generation changed. mohor 7917d 01h /ethmac/tags/rel_23/rtl/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7917d 01h /ethmac/tags/rel_23/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7919d 02h /ethmac/tags/rel_23/rtl/
120 Unused files removed. mohor 7919d 03h /ethmac/tags/rel_23/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7919d 03h /ethmac/tags/rel_23/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.