OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] - Rev 239

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7832d 12h /ethmac/tags/rel_24/
238 Defines fixed to use generic RAM by default. mohor 7844d 16h /ethmac/tags/rel_24/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7846d 21h /ethmac/tags/rel_24/
235 rev 4. mohor 7847d 12h /ethmac/tags/rel_24/
234 Figure list assed to the revision 3. mohor 7847d 20h /ethmac/tags/rel_24/
233 Revision 0.3 released. Some figures added. mohor 7847d 20h /ethmac/tags/rel_24/
232 fpga define added. mohor 7852d 15h /ethmac/tags/rel_24/
231 Description of Core Modules added (figure). mohor 7854d 17h /ethmac/tags/rel_24/
229 case changed to casex. mohor 7858d 13h /ethmac/tags/rel_24/
227 Changed BIST scan signals. tadejm 7858d 17h /ethmac/tags/rel_24/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7858d 19h /ethmac/tags/rel_24/
225 Some minor changes. tadejm 7858d 19h /ethmac/tags/rel_24/
224 Signals for a wave window in Modelsim. tadejm 7858d 20h /ethmac/tags/rel_24/
223 Some code changed due to bug fixes. tadejm 7858d 20h /ethmac/tags/rel_24/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7862d 18h /ethmac/tags/rel_24/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7865d 19h /ethmac/tags/rel_24/
218 Typo error fixed. (When using Bist) mohor 7865d 21h /ethmac/tags/rel_24/
217 Bist supported. mohor 7865d 21h /ethmac/tags/rel_24/
216 Bist signals added. mohor 7865d 21h /ethmac/tags/rel_24/
215 Bist supported. mohor 7865d 22h /ethmac/tags/rel_24/
214 Signals for WISHBONE B3 compliant interface added. mohor 7866d 17h /ethmac/tags/rel_24/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7866d 18h /ethmac/tags/rel_24/
212 Minor $display change. mohor 7866d 18h /ethmac/tags/rel_24/
211 Bist added. mohor 7866d 18h /ethmac/tags/rel_24/
210 BIST added. mohor 7866d 18h /ethmac/tags/rel_24/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7867d 21h /ethmac/tags/rel_24/
208 Virtual Silicon RAMs moved to lib directory tadej 7883d 15h /ethmac/tags/rel_24/
207 Virtual Silicon RAM support fixed tadej 7883d 15h /ethmac/tags/rel_24/
206 Virtual Silicon RAM added to the simulation. mohor 7883d 15h /ethmac/tags/rel_24/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7883d 16h /ethmac/tags/rel_24/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.